Over four years ago, Intel started to develop what is now known as Compute Express Link (CXL), an interface to coherently connect CPUs to all types of other compute resources. Over time, Intel collaborated with other industry behemoths, and early this year nine companies organized the CXL Consortium to jointly develop the technology as a new open standard. Over the past few months, dozens of additional companies have joined the consortium, and now the consortium itself has been formally incorporated this week, marking a major step in the development of CXL as an industry standard.
While incorporation itself doesn't change matters for CXL from a technical perspective, incorporating a group like the CXL Consortium is a fairly big deal, because this typically only happens with an industry standards group gets large enough and gains enough traction that its members are very confident the technology is soon to go into widespread use. This means that the CXL Consortium has been elevated to the same level as the USB-IF, VESA, and other standard groups. Which is to say, all signs point to CXL eventually winning the war of cache-coherent interconnects, and becoming a major, long-term industry standard.
Meanwhile, wasting no time, the newly-incorporated organization has named five additional members of its board of directors, and it has released version 1.1 of the CXL specification.
Support Growth & New BOD Members
Being a CPU-to-everything cache-coherent interconnect protocol, CXL competes in one way or another against such technologies as CCIX, Gen-Z, Infinity Fabric, NVLink, and OpenCAPI, so broad industry support is tremendously important for the technology. Originally founded by Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, Intel, and Microsoft, the CXL Consortium has gained over 50 additional members over the past few months. The consortium now counts nearly 70 companies and organizations in its ranks, from developers of CPUs, GPUs, FPGAs, SSDs, interconnects, servers, and other hardware as well as from software developers and cloud service providers.
Among the companies that recently joined the CXL Consortium are AMD, Arm, IBM, and Xilinx. To that end, the organization appointed five new members to its board of directors from AMD, Arm, IBM, Microchip, and Xilinx. The expanded board of directors now includes 13 members and looks as follows.
| CXL Consortium: Members of the Board | ||||
| Company | Person | Position | ||
| Alibaba | Di Xu | ? | ||
| AMD | Nathan Kalyanasundharam | Senior Fellow at AMD | ||
| Arm | Dong Wei | Standards Architect and Fellow | ||
| Cisco | Sagar Borikar | Principal Engineer, Data Center Systems Engineering | ||
| Dell EMC | Kurtis Bowman | Director of Technology and Architecture in Dell's Server CTO Office | ||
| Chris Petersen | Hardware Systems Technologist | |||
| Rob Sprinkle | Technical Lead for Platforms Infrastructure at Google | |||
| HPE | Barry McAuliffe | ? | ||
| IBM | Steve Fields | Fellow and Chief Engineer of Power Systems | ||
| Intel | Jim Pappas | Director of Technology Initiatives, Intel's Data Center Group. | ||
| Microchip | Larrie Carr | Fellow, Technical Strategy and Architecture, Data Center Solutions | ||
| Microsoft | Leendert van Doorn | Distinguished Engineer | ||
| Xilinx | Gaurav Singh | Corporate Vice President | ||
CXL 1.1 Published
Back in March, the nine founding members of the CXL Consortium published version 1.0 of the specification. By now, several refinements have been made, so this week the organization published version 1.1 of the spec. Unfortunately, the organization does not publicly disclose what changes it brings; though coming this soon after 1.0, it's likely little more than minor tweaks to address underdefined behavior and satisfy the needs of some of the new members.
As a refresher, CXL is designed to enable heterogeneous processing (by using accelerators) and memory systems (think memory expansion devices), the low-latency CXL runs on PCIe 5.0 PHY stack at 32 GT/s and supports x16, x8, and x4 link widths natively. CXL supports three protocols within itself: the mandatory CXL.io as well as CXL.cache for cache coherency, and CXL.memory for memory coherency that are needed to effectively manage latencies. When it comes to performance, a CXL-compliant device will enjoy 64 GB/s bandwidth in each direction when installed into a a PCIe 5.0 x16 slot. In addition, the protocol also supports degraded mode at 16.0 GT/s and 8.0 GT/s data rates as well as x2 and x1 links.
Related Reading:
- Arm Joins CXL Consortium
- AMD Joins CXL Consortium: Playing in All The Interconnects
- Compute Express Link (CXL): From Nine Members to Thirty Three
- CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel
Source: CXL Consortium
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