In what’s quickly becoming a very busy week for data center and high-performance computing news, the PCI Special Interest Group (PCI-SIG) is hosting its annual developers conference over in Santa Clara. The annual gathering for the developers and ecosystem members of the industry’s preeminent expansion bus offers plenty of technical sessions for hardware devs, but for outsiders the most important piece of news to come from the show tends to be the SIG’s annual update on the state of the ecosystem. And this year is no exception, with a fresh update on the development status of PCIe 7.0, as well as PCIe 6.0 adoption and cabling efforts.
With PCI Express 6.0 finalized early last year, the PCI-SIG quickly moved on to starting development work on the next generation of PCIe, 7.0, which was announced at last year’s developer’s conference. Aiming at a 2025 release, PCIe 7.0 aims to once again double the amount of bandwidth available to PCIe devices, bringing a single lane up to 16GB/second of full-duplex, bidirectional bandwidth – and the popular x16 slot up to 256GB/second in each direction.
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