Intel: Meteor Lake Chiplet SoC Up and Running

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Alongside Intel’s regular earnings report yesterday, the company also delivered a brief up on the state of one of their most important upcoming products, Meteor Lake. Intel’s first chiplet/tile-based SoC, which completed initial development last year, has now completed power-on testing and more. The news is not unexpected, but for Intel it still marks a notable milestone, and is important proof that both Meteor Lake and the Intel 4 process remain on track.

Meteor Lake, which is slated to be the basis of Intel’s 14^th generation Core processors in 2023, is an important chip for the company on several levels. In terms of design, it is the first chiplet-based (or as Intel likes to put it, “disaggregated”) mass-market client SoC from the company. Intel’s roadmap for the Core lineup has the company using chiplet-style SoCs on a permanent basis going forward, so Meteor Lake is very important for Intel’s design and architecture teams as it’s going to be their first crack at client chiplets – and proof as to whether they can successfully pull it off.

Meanwhile Meteor Lake is also the first client part that will be built on the Intel 4 process, which was formerly known as Intel’s 7nm process. Intel 4 will mark Intel’s long-awaited (and delayed) transition to using EUV in patterning, making it one of the most significant changes to Intel’s fab technology since the company added FinFETs a decade ago. Given Intel’s fab troubles over the past few years, the company is understandably eager to show off any proof that its fab development cycle is back on track, and that they are going to make their previously declared manufacturing milestones.

As for this week’s power-on announcement, this is in-line with Intel’s earlier expectations. At the company’s 2022 investor meeting back in February, in the client roadmap presentation Intel indicated that they were aiming for a Q2’22 power-on.

We have officially powered-on our first disaggregated product: Meteor Lake. An incredible milestone resulting from the efforts of so many across @intel. Congratulations, team! pic.twitter.com/eKvHzDqSiu

— Michelle Johnston Holthaus (@MJHolthaus) April 29, 2022

In fact, it would seem that Intel has slightly exceeded their own goals. While in a tweet put out today by Michelle Johnston Holthaus, the recently named EVP and GM of Intel’s Client Computing Group, announced that Meteor Lake had been powered on, comments from CEO Pat Gelsinger indicate that Meteor Lake is doing even better than that. According to Gelsinger’s comments on yesterday’s earnings call, Meteor Lake has also been able to boot Windows, Chrome, and Linux. So while there remains many months of bring-up left to go, it would seem that Meteor Lake’s development is proceeding apace.

But that will be a story for 2023. Intel will first be getting Raptor Lake out the door later this year. The Alder Lake successor is being built on the same Intel 7 process as Alder Lake itself, and will feature an enhanced version of the Alder Lake architecture.

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Intel Reports Q1 2022 Earnings: Improved Enterprise Sales Buoy Weaker Client Revenue

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Kicking off our coverage of the first earnings season of the year for the tech industry, we as always start with Intel. The blue-hued blue-chip company is the first out of the gate to report their results for the first quarter of 2022, with Intel reporting something of a mixed quarter. With revenue down on a yearly basis – thanks in large part to softer client sales – Intel is no longer on a hot streak of setting records. At the same time, however, the company has dialed back its lofty expectations accordingly, and as a result was still able to slightly edge out its Q1 guidance.

For the first quarter of 2022, Intel booked $18.4B in revenue, a drop of 7% from the year-ago quarter. Buffering the company against this revenue drop on a GAAP basis has been an improvement in both operating income and net income, both of which benefitted from some one-off restructuring and investment gains (McAfee equity sale). As a result, Intel booked $8.1B in net income on a GAAP basis, which is a 141% improvement on the year. Otherwise, stripping things back to non-GAAP financials, things more closely mirror the overall revenue picture with a 35% decline in income.

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Nvidia could make a surprising move with RTX 4000 GPUs

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Nvidia might stick with the PCIe 4.0 interface with its next-gen Lovelace graphics cards, according to a fresh rumor.

This comes from a prominent hardware leaker on Twitter, Kopite7kimi, who spilled a couple of fresh nuggets of info in some recent tweets about what will presumably be RTX 4000 GPUs (though Nvidia could depart from the obvious next step for the name).

PCIe Gen4April 24, 2022

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Existing Nvidia RTX 3000 GPUs (Ampere) use a PCIe 4.0 slot in the motherboard, but with Lovelace, Nvidia was thought to be possibly stepping up to PCIe 5.0.

Mainly because Nvidia is adopting PCIe 5.0 with Hopper, its next-gen heavyweight (data center) GPUs, so it’d follow to some extent that Team Green might look to shift the incoming consumer graphics cards in that same direction. At the very least from a marketing point of view, particularly now that PCIe 5.0 is provided by Intel with the 12th-gen Alder Lake range, and the cutting-edge standard is expected to be adopted by AMD with next-gen Zen 4 processors that should debut later in 2022 (which is when Lovelace is scheduled to arrive).

Furthermore, Nvidia is expected to use PCIe 5.0 power connectors with the RTX 4000 range – as already seen with the RTX 3090 Ti, in fact, given the GPU’s heavy power demands – so Lovelace will theoretically use PCIe 5.0 for power, but stick with that PCIe 4.0 interface.

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Analysis: Will we really need PCIe 5.0 before RTX 5000, anyway?

While this might seem like an unusual situation to have a graphics card with PCIe 5.0 power but slotted into a PCIe 4.0 interface, it’s not really that surprising when you think about it more. As mentioned, the new 3090 Ti already does this, and is purportedly a test drive of sorts for RTX 4000 cards, if the rumor mill is to be believed (as Neowin, which reported on this, points out). Naturally, all of this remains speculation, so let’s not get carried away – we’re cautious about how much stock to put in this fresh rumor anyway.

Still, it does make sense that Nvidia might want to keep PCIe 4.0 for the next-generation purely from a practical point of view. It would cost more to equip Lovelace graphics cards with the cutting-edge PCIe 5.0 interface, and to no real end – PCIe 4.0 already offers plenty of bandwidth.

While PCIe 5.0 would provide future-proofing, of course, realistically by the time PCIe 4.0 is struggling to cope with gaming demands, Nvidia will likely be releasing RTX 5000 cards – and those can come with the PCIe 5.0 interface.

In short, it doesn’t feel like there’s a compelling need to step up to PCIe 5.0 just yet, and the cost savings of sticking with PCIe 4.0 can likely be put to better use elsewhere in terms of juicing up Lovelace performance. So we won’t be particularly surprised if this turns out to be the case, or worried for that matter – the real concern about the RTX 4000 family for us is those rumors around huge levels of power consumption.

With tales of Lovelace graphics cards pushing power usage up to 600W, or maybe even further – like 800W at the flagship level – this is definitely the biggest worry around the next-gen GPUs. What gamers don’t want is a situation where they have to think about upgrading their power supply as well as buying a new graphics card (with GPUs being more than expensive enough already, though at least inflated prices are finally coming down in recent times).

• About that new RTX 3090 Ti – how good is it really, and how heavy is that power usage?

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TSMC Roadmap Update: N3E in 2024, N2 in 2026, Major Changes Incoming

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Taiwan Semiconductor Manufacturing Co. has solid plans for the next few years, but the foundry's manufacturing technology design cycles are getting longer. As a result, to address all of its clients' needs, the company will have to keep offering half-nodes, enhanced, and specialized versions of its fabrication processes.

TSMC's success in the last 20 years or so was largely conditioned by the company's ability to offer a new manufacturing technology with PPA (power, performance, area) improvements every year and introduce a brand-new node every 18 – 24 months while maintaining predictably high yields. But as complexity of modern fabrication processes gets to unprecedented levels, it is getting much harder to keep the pace of innovation while also sustaining predictable yields and simple design principles.

With TSMC's N3 node, the gap between N5 (5 nm-class) ramp up and N3 (3 nm-class) ramp up will increase to around 2.5 years, which may pose some challenges to the foundry's key customer, Apple. The good news is that N3's follow up, N3E, seems to be coming in ahead of schedule. Meanwhile, with N2, the cadence is set to stretch to about three years, which largely means a strategic shift in TSMC's strategy of node development. 

N3E: An Improved 3nm Node Pulled In (Almost)

TSMC's N3 is set to bring in full node improvements over N5, which includes 10% ~ 15% more performance, 25% ~ 30% power reduction, and an up to 1.7X higher transistor density for logic. To do so, it will use more than 14 extreme ultraviolet (EUV) lithography layers (N5 uses up to 14, and N3 is expected to use even more) and will introduce certain new design rules for deep ultraviolet lithography (DUV) layers. 

Advertised PPA Improvements of New Process Technologies Data announced during conference calls, events, press briefings and press releases
	TSMC
	N7 vs 16FF+	N7 vs N10	N7P vs N7	N7+ vs N7	N5 vs N7	N5P vs N5	N3 vs N5
Power	-60%	<-40%	-10%	-15%	-30%	-10%	-25-30%
Performance	+30%	?	+7%	+10%	+15%	+5%	+10-15%
Logic Area Reduction % (Density)	70%	>37%	-	~17%	0.55x -45% (1.8x)	-	0.58x -42% (1.7x)
Volume Manufacturing				Q2 2019	Q2 2020	2021	H2 2022

TSMC is set to start ramping up production of chips using its N3 node in the second half of the year and will deliver the first commercial batch to a client (or clients) in early 2023, which is when it will receive the first N3 revenue.

While TSMC's N3 process technology was designed both for high-performance computing (which is a term that TSMC uses to describe applications like CPUs, GPUs, FPGAs, ASICs, etc.) and smartphones in mind, there is evidence that the node has a rather narrow process window, which would make it hard for chip developers to hit desired specifications. This is a problem as it increases time-to-yield and ultimately lowers margins. In an apparent bid to tackle the issue, TSMC has developed N3E version of the technology that widens process window and provides improvements over N5.

"N3E will further extend our N3 family with enhanced performance, power, and yield," said C. C. Wei, chief executive of TSMC.

Originally, TSMC planned to start high-volume manufacturing (HVM) using N3E about a year after N3 (i.e., in Q3 2023), but in the recent months a rumor emerged that TSMC was pulling in HVM of N3E by about a quarter due to better than expected test production runs. During its most recent conference call, TSMC confirmed that N3E's progress was ahead of schedule and that it was considering pulling in mass production using this technology, but did not elaborate about exact plans.

"Our N3E result is quite good," said the head of TSMC. "The progress is ahead of our schedule. And pull-in, yes, we are considering that. So far, I still did not have a very solid data to share with you that how many months we can pull in. But yes, it is in our plan."

Keeping in mind that chip developers have their own schedules for their designs, it is unlikely that all of them will be able to take advantage of earlier N3E ramp since their chips have to pass all the pre-production iterations as well. Nonetheless, better-than-expected N3E progress is a good sign in general, especially considering the fact that TSMC's N3 family will have to serve the industry for quite a long time.

N2: Expect First Chips in 2026

In fact, N3 and its evolutionary iterations will remain TSMC's leading-edge offerings till late 2025 because the company's N2 (2 nm-class) schedule looks quite conservative.

When TSMC first talked about its N2 in August 2020, it did not reveal many details about the technology (by now we know that it adopts gate-all-around [GAA] transistor structure) or its schedule, but indicated that it would build a brand-new fab near Baoshan, Hsinchu County, Taiwan, for this node (some sources call this new facility Fab 20). Taiwanese authorities approved the construction plan in mid-2021 and that plan included breaking ground in early 2022 (earlier this year TSMC's board of directors indeed accepted capital appropriations for a new fab construction), so we believe that the shell is being built as we speak. 

Shell construction usually takes a year or a little more, then equipment installation takes over a year as well, so we expect the first phase of Fab 20 to be ready by mid-2024 at the latest. TSMC expects to start risk production using its N2 technology in late 2024 and then initiate HVM towards the end of 2025, which means that the gap between the initial N3 ramp in Q3 2022 and initial N2 ramp in Q4 2025 will be about three years.

"Our progress so far today for the N2 is on track," said Mr. Wei. "All I want to say is, yes, at the end of 2024, [N2] will enter the risk production. 2025, it will be in production, probably close to the second half or the – or the end of 2025. That is our schedule."

Considering how long modern chip production cycles are, it is safe to say that the first N2 chips made by TSMC will arrive in consumer devices no sooner than early 2026.

TSMC's New Node Introduction in Recent Years
	N7	N7P	N5	N5P	N3	N3E	N2
Transistor Type	FinFET	FinFET	FinFET	FinFET	FinFET	FinFET	GAA FET
Risc Production	?	?	?	?	2021	2022	Late 2024
Volume Manufacturing	Q2 2018	Q2 2019	Q2 2020	Q2 2021	Q3 2022	Q2/Q3 2023	Late 2025

But perhaps TSMC's public disclosures about N2 and Fab 20 are too conservative. Analysts from China Renaissance Securities seem to be more optimistic about Fab 20 readiness than TSMC is, which may be an indicator that the foundry could pull-in N2 HVM by a quarter or even two if the fabrication process meets its performance, power, and yield goals.

"We also see more clarity around TSMC's N2 expansion schedule in Fab 20 (Hsinchu)," Sze Ho Ng, an analyst with China Renaissance Securities, wrote in a report for clients. "Tool move-in is expected to start by end-2022, based on company plans, ahead of risk production in late 2024E with Intel (client PC Lunar Lake's graphic 'tiles', while the CPU 'tiles' are fabbed using Intel’s 18A) and Apple being the anchor customers for dedicated capacity support."

Meanwhile, pulling in a node from Q4 2025 to Q3 2025 when alpha customers already set their plans for 2025 may not make a lot of sense, but we will certainly see how things work out with N2.

More N3 Iterations

This year, TSMC's customers that need a leading-edge fabrication process will use the company's N4 technology, which belongs to the N5 family (along with N5, N5P, N4P, and N4X). Essentially, this means that an N5 node will remain TSMC's most advanced offering for three consecutive years.

N3 nodes will also have to serve TSMC's clients for another three years (2023, 2024, 2025), so we are going to see several iterations of this process. So far, TSMC has formally confirmed N3E and N3X (which is another performance-oriented manufacturing technology akin to N4X aimed primarily at CPUs and datacenter ASICs), but I would expect more N3-derived nodes to come to address mainstream SoCs in 2024 ~ 2025. 

Keeping in mind that TSMC's FinFET-based N3 will have to stay competitive against GAA-based Samsung's 3GAP and 2GAE/2GAP in 2023 ~ 2025 and Intel's 20A (RibbonFET + PowerVia) in 2024 and 18A (High-NA EUV) in 2025, TSMC's engineers will have to be quite creative with their N3 enhancements. 

On the foundry side of things, TSMC will remain ahead of its rivals for quite a while since Intel is not expected to invest significantly in its IFS-dedicated capacity before 2025 (so its 20A and 18A capacities for IFS customers will likely be limited), whereas Samsung Foundry is traditionally behind TSMC when it comes leading-edge capacity and prefers to prioritize its parent company and strategic clients (e.g., Qualcomm). But formal process technology leadership is what TSMC's engineers will have to maintain with N3 and it will be uneasy to do considering how aggressive Intel and Samsung are.

Changes Are Coming

Evidently, TSMC's brand-new process development and ramp up cadence has increased to two-and-a-half years with N3 and will increase to three years with N2, which may be considered as a major slowdown by its key customers. Meanwhile, potential pull-in of N3E is a good sign which shows that the company can make its intra-node advancements fairly quickly. Hence, the main question is how significant will TSMC's intra-node advancements be going forward. This is a question that only time will answer.

In the meantime, it looks like with TSMC's three-year new node development cycle, future intra-node advancements will be significantly more important for the company and its clients than they are today.

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Intel Raptor Lake CPUs could outgun AMD with rumored boost of up to 5.8GHz

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Intel’s Core i9-13900K, its next-gen flagship processor (presumably), could hit seriously fast Turbo speeds a good chunk higher than even the mighty 12900KS manages.

The Core i9-12900KS is the freshly released supercharged variant of the 12900K, and the CPU can boost to 5.5GHz right out of the box.

However, in theory, Intel’s 13th-gen Raptor Lake silicon will be capable of taking clock speeds 200MHz or 300MHz faster than this, as rumored by hardware leaker Raichu on Twitter.

RPL will over the new highest freq which was created by 12900KS.More 2-300 MHz is possible.April 13, 2022

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In theory, then, the Raptor Lake flagship could end up hitting 5.7GHz or 5.8GHz, which would be pretty staggering speeds straight off the bat with no tweaking or knowledge of overclocking needed.

We’re talking about the boost for the CPU’s performance cores of course – the efficiency cores would run slower, as ever – and furthermore, the maximum speed for a pair of cores, too (you won’t get full pelt across all-cores, naturally; with the 12900KS, all-core boost tops out at 5.2GHz, 300Hz shy of the max Turbo).

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Analysis: Raptor Lake could deliver quite a punch – but will Zen 4 land the first blow?

What isn’t clear is if when Raichu talks about Raptor Lake reaching these heights, whether they’re referring to the Core i9-13900K, or an eventual 13900KS higher-binned variant – if Intel even takes that route. (It doesn’t always make a ‘KS’ edition of the flagship, and in fact the last one before the 12900KS was the 9900KS, so three generations back).

Whatever the case, based on this rumor, the broad expectation is that we can anticipate Raptor Lake delivering a significant boost to clock speeds, and of course that won’t be all. A new generation will inevitably bring an IPC uplift (more Instructions per Clock means you get even more out of faster clock speeds), and even if Raptor Lake is only a straight refresh of Alder Lake, it has some interesting trimmings on the side. Like a major on-board cache boost to pep up gaming frame rates, for example.

Let’s not forget that the 13900K is rumored to be upping the efficiency cores from 8 to 16 (while keeping the same 8 performance cores), so the flagship CPU will theoretically be a 24-core affair (with 32-threads, as efficiency cores don’t have hyper-threading). And that should give the CPU a little more oomph, too.

The upshot is that despite being just a basic refresh in theory, Raptor Lake could smooth out any rough edges in Alder Lake – which is Intel’s first real foray into hybrid cores, of course, Lakefield aside – to deliver quite a punch. Let’s hope so, although the other question here is whether AMD will get the first blow in by launching Zen 4 before Raptor Lake.

While Intel’s Raptor Lake has been rumored for a Q3 debut (multiple times), that’s not certain, and other speculation has contended that AMD may also be shooting to get next-gen Zen 4 processors out in Q3, possibly aiming to beat Intel to market. Which, to be fair, Team Red really needs to do if possible, because if Intel’s 13th-gen range turns up first, AMD’s Ryzen 5000 series is going to be left looking rather underpowered indeed.

• Want to build a decent gaming PC but not spend a fortune? Check out our advice here

Via Wccftech

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Broadcom Launches Wi-Fi 7 Portfolio for Access Points and Client Devices

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The last few years have seen heightened consumer focus on wireless networking. The industry has also been quite busy, enabling the operation of Wi-Fi 6 (802.11ax) in the 6GHz band with Wi-Fi 6E. In parallel, the 802.11 Working Group had started work on 802.11be with a focus on extremely high throughput (EHT). Wi-Fi 7 is set to become the consumer-facing moniker for 802.11be.

802.11be aims to achieve high throughput primarily through a combination of three aspects:

• Support for up to 16 spatial streams
• Support for 320MHz-wide channels (with operation in 2.4 GHz, 5 GHz, and 6 GHz bands)
• Support for 4096-QAM (4K-QAM) resulting in better utilization of available spectrum (a faster modulation / coding scheme).

Theoretically, these aspects allow for up to around 46 Gbps of wireless throughput. 802.11be also aims to enable usage of Wi-Fi for real-time applications by including features for low-latency communications such as Multi-link operation (MLO). This allows a client and an access point to simultaneously communicate over multiple channels that might even belong to different bands. Interference and co-existence with non-Wi-Fi users of the same spectrum is handled using automatic frequency coordination (AFC).

A number of additional features targeting these two thrust areas are under consideration for the final standard. However, multiple silicon vendors have already started introducing silicon supporting variations of the aspects included in the first 802.11be draft specifications.

Mediatek was one of the first vendors to demonstrate working 802.11be-compliant silicon earlier this year. Though Mediatek indicated that the products would be marketed under the Filogic lineup, concrete technical details and part numbers were not announced. At MWC 2022, Qualcomm provided details of their 802.11be client silicon targeting mobile devices. The FastConnect 7800 is expected to become available in H2 2022, and integrates Bluetooth 5.3 support with key Wi-Fi 7 features.

Broadcom is announcing a comprehensive portfolio of products targeting various Wi-Fi 7 markets today.

The table below summarize the key features of the products targeting access points. All of these support 4K-QAM and Multi-Link Operation.

Broadcom 802.11be (Wi-Fi) Access Point Radios Specifications
	BCM67263	BCM6726	BCMN43740	BCMN43720
Target Market	Residential Wi-Fi APs		Enterprise Wi-Fi APs
Operational Band	6 GHz	2.4 GHz (or) 5 GHz (or) 6 GHz
Stream Count	4			2
Max. Channel Width	320 MHz	160 MHz	320 MHz	160 MHz
PHY Rate	11.5 Gbps	5.75 Gbps	11.5 Gbps	2.88 Gbps

The AP products support AFC in order to ensure that 6GHz range is not affected (the APs are mandated to receive regularly scheduled clearance from a central authority to prevent interference with 6 GHz spectrum users). Broadcom has applied to be an AFC operator and will offer AFC service with their chips. This will use Open AFC code. Broadcom also believes a vibrant Wi-Fi 7 ecosystem requires an AFC service that the device makers can use independent of the chip vendor. Organizations such as the Wi-Fi Alliance, and Wireless Broadband Alliance have applied to be AFC operators, with Open AFC already gaining traction in this.

Tying these together in Broadcom's Wi-Fi 7 router reference design is the BCM4916 network processor. This ARM v8-compatible quad-core SoC includes a dual-issue Runner packet processor (DI-XRDP), an integrated NBASE-T (up to 10G) Ethernet PHY for WAN or LAN, four integrated 1GbE PHYs, three USXGMII interfaces, multiple USB ports, and a 32-bit DDR3/DDR4 DRAM interface.

The quad-core CPU is a custom Broadcom design with 64KB of L1 cache and 1MB of L2 cache, providing up to 24K DMIPS horsepower. Without the knowledge of exact clock speeds, it is difficult to compare against the standard Cortex cores from ARM. Based on the DMIPS number, this appears to slot in-between a Cortex-A53 and an A57, but does not include the ARM v8.2 features of the A55.

Broadcom's customers can play around with the radio configuration in the above design to create products at different price points. Tri-band support becomes compulsory in Wi-Fi 7. The extremely high throughput enabled by this means that 10G support on the WAN/LAN side and NBASE-T support on the LAN front will become the de-facto standard for routers and APs in the coming years.

Broadcom is also introducing the BCM4398 - an integrated Wi-Fi 7 and Bluetooth 5 combo chip targeting smartphones and other mobile applications. It supports two streams of Wi-Fi 7, channel width of up to 320 MHz, and a 6.05 Gbps PHY rate. On the client side, one of the key user-visible updates is low-latency operation. Broadcom claims that the BCM4398 can achieve sub-millisecond latencies for lightly congested environments in the 6 GHz band. The client multi-link operation feature can keep both uplink and downlink latencies between 5 and 10ms in situations where both 5 and 6 GHz bands are highly congested. This provides determinism for AR/VR knowing that worst case latencies will be down to a few milliseconds even during heavy congestion.

Broadcom is the first vendor to announce a complete portfolio of Wi-Fi 7 products, with sampling for key customers already in progress. The new products should give end-consumers a taste of the values delivered by Wi-Fi 7 for different applications a few quarters from now.

Gallery: Broadcom Launches Wi-Fi 7 Portfolio for Access Points and Client Devices

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Intel Opens D1X-Mod3 Fab Expansion; Moves Up Intel 18A Manufacturing to H2’2024

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Intel for the last few years has been undergoing a major period of manufacturing expansion for the company. While the more recent announcements of new facilities in Ohio and Germany have understandably taken a lot of the spotlight – especially given their importance to Intel’s Foundry Services plans – Intel has been working even longer on expanding their existing facilities for their own use. The company’s development of next-generation EUV and Gate-All-Around-style transistors (RibbonFET) not only requires creating and refining the underlying technology, but it also just flat out requires more space. A lot of it.

To that end, Intel today is holding a grand opening in Oregon for the Mod3 expansion of D1X, the company’s primary development fab. The expansion, first announced back in 2019, is the third such mod (module) and second expansion for Intel’s main dev fab to be built since D1X’s initial construction in 2010. And in keeping with tradition for Intel fab launches and expansions, the company is making something of an event of it, including bringing Oregon’s governor out to show off their $3 Billion investment.

But fanfare aside, the latest mod for the fab is a genuinely important one for Intel: not only does it add a further 270,000 square feet of clean room space to the facility – expanding D1X by about 20% – but it’s the only fab module that’s big enough to support the High Numerical Aperture (High NA) EUV tool that Intel will be using starting with its 18A process. ASML’s forthcoming TWINSCAN EXE:5200 EUV tool is designed to be their most powerful yet, but it’s also quite a bit larger than the NXE 3000 series EUV tools Intel is using for their first generation EUV processes (Intel 4/3). It’s so big that D1X’s ceiling is too low to fit the machine, never mind support its weight.

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AMD GPU driver bug reportedly messes with some Ryzen CPUs, with users unaware

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AMD’s graphics driver has been observed to mess with certain CPU settings according to fresh reports, in what can only be described as a very odd affair.

This comes from Igor’s Lab (via Tom’s Hardware), with the German tech site pointing out that the apparent problem was highlighted by a reader, and Igor subsequently managed to reproduce the issue in one case (with AMD hardware owners detailing their further findings on Reddit).

To sum up the current speculation around this – and remember, this is still just speculation, so let’s be cautious about what we can conclude here – the theory is that the integration of AMD’s Ryzen Master tool into the Adrenalin version 22.3.1 graphics driver (or later) is causing the issue, whereby a Ryzen CPU is witnessing changes to boost settings unknown to the user.

As we said at the outset, this is certainly a strange state of affairs, though it only happens to those who install the Radeon driver who also have an AMD Ryzen CPU (Ryzen Master is an overclocking module designed to allow for pepping up the processor’s performance in a user-friendly manner, in case you weren’t aware).

What’s supposedly happening is that when the new Adrenalin graphics driver is installed on a system, when applying a GPU profile the software can apparently change the PBO (precision boost, or overclocking) setting in the BIOS, putting it back to the default (if the user previously altered it).

Or so the theorizing runs, anyway, and this could obviously be problematic in some situations, and as Igor points out, could lead to the PC crashing. As mentioned, a further issue is that the user isn’t told about these changes being applied, so they could end up pretty confused as to why they’re suddenly having trouble with their system.

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Analysis: Multiple workarounds have been floated

This is an unfortunate situation, of course, and hopefully, AMD will now be investigating these reports, and Team Red will subsequently be able to take appropriate action.

Meanwhile, there are a few ways that you can work around the problem. The first and most obvious is simply to head back to your BIOS post-installation of the new graphics driver, and reconfigure your old settings (or for those who run default settings anyway, just disable PBO).

Another suggestion in the above Reddit thread is not to load older profiles, but to create a new tuning profile for the graphics card instead. Electrical-Bobcat435 advises: “It’s a small headache, reproducing clocks and fan curves, but once done, it won’t reboot/change bios PBO settings. It's absurd that AMD did this but there’s the workaround.”

Finally, as Igor’s Lab and again someone else on Reddit suggests, there’s the Radeon Software Slimmer utility which can be used to remove Ryzen Master from the Adrenalin driver, thereby stopping the tool from interfering with the CPU. However, this is a third-party program, so it’s installed entirely at your own risk.

• Want better GPU performance for free? We’ll show you how to overclock your graphics card

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The ADATA XPG Levante 360 AIO Cooler Review: Stuck in the Middle

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A few weeks ago we had a look at ADATA's first attempt into the PC Power Supply market with the Cybercore PSU. In today's review we are checking out another of their diversification attempts, this time towards the CPU cooling market, in the form of the XPG Levante 360 all-in-one liquid cooler. Heavily based on an Asetek reference design, the XPG Levante 360 is a very well performing and well built cooler, but it struggles to stand out in a commodity market full of CPU coolers.

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